1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a silicon layer having an impurity diffusion preventing layer therein.
2. Description of the Related Art
In a semiconductor device, a polycrystalline silicon layer has been used as an electrode, a contact structure, and the like. This polycrystalline silicon layer is grown by a chemical vapor deposition (CVD) method or a sputtering method. After that, impurities such as phosphorus and arsenic are introduced by a diffusion method or an ion-implantation method into the polycrystalline silicon layer, thereby reducing the resistance thereof.
On the other hand, as semiconductor devices have been reduced in size, when the above-mentioned polycrystalline silicon layer is formed as a gate electrode on a gate insulating layer, the impurities included in the polycrystalline silicon layer are diffused into the gate insulating layer by a heat operation carried out at a post stage, thus changing the property of the gate insulating layer. Similarly, when the above-mentioned polycrystalline silicon layer is formed as a contact structure on a semiconductor substrate, the impurities included in the polycrystalline silicon layer are diffused into an impurity diffusion region within the semiconductor substrate by a heat operation carried out at a post stage, thus enlarging the impurity diffusion region.
In order to prevent impurities from being diffused into the gate insulating layer or the impurity diffusion region, an impurity diffusion preventing layer is formed in the polycrystalline silicon layer (see JP-A-HEI4-162675 and JP-A-HEI2-45930). That is, first, a first polycrystalline silicon layer is grown. Then, a native silicon oxide layer is formed on the first polycrystalline silicon layer, or a silicon oxide layer is grown by supplying Ar gas including oxygen to a CVD apparatus. Then, a second polycrystalline silicon layer is grown on the native silicon oxide layer or the grown silicon oxide layer in the same CVD apparatus, and thereafter, impurities are doped into the second polycrystalline silicon layer. In this case, the concentration of impurities of the first polycrystalline silicon layer is smaller than that of the second polycrystalline silicon layer, thus suppressing the diffusion of impurities into the gate insulating layer or impurity diffusion region.
In the above-mentioned prior art method, however, when an aspect ratio of the gate electrode or the contact structure has become larger, for example, when a contact structure having a radius of 0.4 .mu.m and a height of 1 .mu.m is formed in a 256 Mbit dynamic random access memory (DRAM) device, impurities are hardly doped into the contact structure. Therefore, a step of growing a polycrystalline silicon layer having a thickness of several hundreds of .ANG. to 1000 .ANG. and a step of doping impurities thereinto have to be repeated a plurality of times, thus increasing the manufacturing cost.